I'd compare this to Unison [1,2] where they combine register allocation and instruction scheduling into a single phase using combinatorial optimization. Usually you have to choose one before the other.

[1] http://llvm.org/devmtg/2017-03//assets/slides/register_alloc...

[2] https://www.sics.se/~rcas/publications/CastanedaCarlssonEa_C...