>Honestly, even C execution could probably be speeded up by having separate stack and heap memory pipelines.
Later versions of Alpha AXP architecture did almost exactly that. They reorder memory access based on addresses. Alpha could execute load after store without blocking, providing load address did not clash with store address.
It helped them a lot, given that they had 80 registers at their disposal.
Any modern x86 processor can do that too. The thing is, the complexity of the circuitry involved increases faster than linearly so being able to break it out into two sets of load/store queues would let you increase bandwidth by a fair bit.
Later versions of Alpha AXP architecture did almost exactly that. They reorder memory access based on addresses. Alpha could execute load after store without blocking, providing load address did not clash with store address.
It helped them a lot, given that they had 80 registers at their disposal.