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I had never looked at a GPU this way before, but it's essentially a "slocket". The name comes from the Pentium II and some Celerons, which mounted onto an addon card which also carried the external L2 RAM cache. This was mounted on the daughterboard to grant physical proximity and thus low latency. http://en.wikipedia.org/wiki/Pentium_II

Does this count as a 3DIC?

Also, obligatory: http://i.imgur.com/v7loIkF.jpg

I've seen GPUs advertised as having 128-bit buses, but I didn't know GDDR5 was only 32bit. For this it feels a bit like the RAMBUS vs DDR battle all over again; high-clock combined with a narrow bus caused higher latencies than a slower clock with a wider bus, which has the added benefit of being cheaper overall.



A slocket is a PCB with an edge connector, just like current graphics cards.

This is a multi-chip module or MCM (http://en.wikipedia.org/wiki/Multi-chip_module). Intel also uses them to put the North bridge on the same package as the CPU for its mobile CPU's.

There are several innovative aspects about this MCM, but MCM's have been around for a long time.

A single GDDR5 chip is 32bit. GPU's use many chips in parallel to achieve wider buses.


I guess the difference here is the substrate is another silicon chip rather than PCB or substitute. Pretty cool. Must have been some significant engineering challenges.




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